1. Field of the Invention
This invention relates to a semiconductor device and to a method for manufacturing the same. In particular, the present invention relates to a MOSFET which has side wall structure and to a method for manufacturing the same.
This is a counterpart of, and claims priority to, Japanese Patent Application No. 2000-010250, filed on Jan. 17, 2000, the contents of which are incorporated herein by reference.
2. Description of the Related Art
A Self-Aligned Contact (SAC) method is an important technique used in fabricating semiconductor devices. This technology is described in the article entitled “A Process Technology for 1 Giga-Bit DRAM” IEDM Tech. Dig., pp 907–910, 1995.
SiN is generally used as sidewalls of a gate electrode in the SAC process.
This is because the etching rate of SiN is different from that of silicon-oxide, and therefore SiN sidewalls are used as a stopper in etching on an intermediate oxide layer.
FIG. 23 is a schematic diagram of a MOSFET 800 manufactured using an SAC process.
A gate oxide layer 824 having a constant thickness is formed on a silicon substrate 802. A gate electrode 816 is formed on the gate oxide layer 824. A SiN cap layer 820 is formed on the gate electrode 816. SiN sidewalls 822, which cover the side surfaces of the gate electrode 816, are formed on the gate oxide layer 824.
A heat treatment is generally performed in manufacturing of the MOSFET 800 after the formation of sidewalls. In case of SiN sidewalls, hydrogen and nitrogen may be diffused into the silicon substrate 802 through the gate oxide layer 824 during the heat treatment. Therefore, MOSFETs which have SiN sidewalls are less reliable due to resultant hot-carrier degradation than MOSFETs which have sidewalls of silicon oxide. These problems are pointed out and discussed in the article entitled Enhancement of Hot-Carrier Induced Degradation under Low Gate Voltage Stress due to Hydrogen for NMOSFETs with SiN films” S. Tokitoh et al. IRPS, pp 307–311, 1997 and “Hot-carrier Degradation Mechanism and Promising Device Design of nMOSFETs with Niteride Sidewall Spacer” Y. Yamasugi. et al. IRPS, pp 184–188, 1998.